In recent years, in line with the development of downsized and high-performance electronic devices such as computers and communication devices, a downsizing, a higher density and a speedup have been required of the semiconductor device. Therefore, semiconductor devices referred to as a three-dimensional chip formed by stacking a plurality of semiconductor chips, which are downsized and become high-density, are proposed. As a method of stacking a plurality of chips, a method shown in Japanese Unexamined Patent Publication No. 10-223833 is proposed.
Here, steps of producing a conventional semiconductor device will be described by use of FIG. 7. FIGS. 7A to 7J are sectional views of a semiconductor device showing a production process of a conventional semiconductor device.
First, a circuit component portion 51 is formed on the front side of a substrate 50 to obtain a structure shown in FIG. 7A. Next, a photoresist layer is formed by applying a photoresist onto the front side of the substrate 50, and a mask layer 52 having an opening 52a is formed by patterning this photoresist layer. Next, the circuit component portion 51 and the substrate 50 composed of a silicon wafer is etched by reactive ion etching (RIE) using the mask layer 52 to form a blind hole 53 with a depth of a little less than 100 μm below the surface of the substrate to obtain a structure shown in FIG. 7B. Next, an insulating film 54 is formed on the inner wall of the blind hole 53 to obtain a structure shown in FIG. 7C. Next, a seed layer 55 to become a cathode of electrolytic plating is formed on the insulating film, and this seed layer is used as a cathode and the inside of the blind hole 53 is filled with metal 56 to obtain a structure shown in FIG. 7D. Next, excess metal outside of the blind hole 53 is removed by chemical and mechanical polishing (CMP) of metal 56 to obtain a structure shown in FIG. 7E. Next, a supporting body 58 is bonded to the circuit component portion 51 side of the substrate 50 with a adhesive layer 57 consisting of a double-faced tape therebetween, and the backside of the substrate 50 is ground to expose metal 56 filled into the blind hole 53 to the backside of the substrate to obtain a structure shown in FIG. 7F. Next, the backside of the substrate 50 is selectively etched to obtain a structure shown in FIG. 7G. Next, an insulating film 59 of SiN or SiO2 is deposited on the backside of the substrate 50 by a chemical vapor deposition (CVD) method to obtain a structure shown in FIG. 7H. Next, the insulating film 59 is removed to expose the metal 56 in the through-hole electrode using a CMP method to obtain a structure shown in FIG. 7I. Next, the supporting body 58 and the adhesive layer 57 are removed to obtain a structure shown in FIG. 7J.
A semiconductor device having a through-hole electrode can be produced by the above-mentioned steps.
In the above-mentioned production method, after the blind hole is filled with metal by electrolytic plating, metal is exposed to the backside of the substrate by thinning a Si substrate, and thereby a through-hole electrode is formed. But, when this method is used, a plating solution is hardly supplied to the bottom of the blind hole in filling the metal into the blind hole, and the metal filling is not completely performed due to hydrogen produced in electrolytic plating and voids tend to be generated. And, in order to perform complete filling, a complicated and sophisticated plating method using an additive is required and a plating time becomes longer. Consequently, there is a problem that a process cost increases.